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Staff DFT DV Engineer, AI Hardware
Tesla
Bengaluru, IND
Full-time
Senior · 10+ years experience
Onsite
Discovered 3 weeks ago
SystemVerilogUVMDFTMBISTJTAGboundary scan
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SystemVerilogUVMDFT
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SystemVerilogUVMDFTMBISTJTAGboundary scan
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Responsibilities
- Develop SystemVerilog/UVM testbenches to verify DFT features — SSN, compressed scan, memory BIST, JTAG, and boundary scan at block and SoC level
- Verify top-level DFT features — power-on self-test, clock observation, clock stop, and scan dump
- Run DV regressions, analyze coverage, triage and debug failures to closure
- Identify design fixes and validate DFT RTL corrections
- Deliver pre-Si DV testcases for silicon bring-up and ATE correlation
- Own post-silicon ATE test correlation — root cause discrepancies between pre-Si and silicon behavior
- Leverage agentic AI flows to automate regression execution, coverage analysis, and failure triage
Requirements
- Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience
- 10+ years of DFT DV experience at block and SoC level
- Expert-level SystemVerilog and UVM testbench development
- Hands-on verification of SSN, compressed scan, MBIST, JTAG, and boundary scan
- Experience delivering pre-Si testcases through silicon bring-up and ATE correlation
- Ability to use agentic AI flows to automate DV regression and debug workflows
- Post-silicon debug and ATE correlation experience on server-class SoCs
- Familiarity with formal verification methods for DFT structural checks
- Experience with power-on self-test and clock control verification
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