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Staff DFT ATPG Engineer, AI Hardware
Tesla
Bengaluru, IND
Full-time
Senior · 10+ years experience
Onsite
Discovered 3 weeks ago
TessentTestKompressMemoryBISTTempusATE test programs
Free
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TessentTestKompressMemoryBIST
Key Skills for This Role
TessentTestKompressMemoryBISTTempusATE test programs
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Responsibilities
- Generate production-quality ATPG patterns using Tessent for stuck-at, transition delay, path delay, cell-aware, and small delay defect (SDD) fault models
- Achieve and exceed coverage targets (>99% stuck-at, >98% transition) while minimizing pattern count for ATE test time
- Debug low coverage areas — X-state sources, blocking logic, untestable faults, and ATPG abort conditions
- Understanding and familiarity of hybrid bonding test concepts
- Perform gate-level pattern simulation to validate pattern integrity
- Support hierarchical and flat ATPG methodologies for multi-million gate SoC designs
- Architect and develop comprehensive ATE test programs covering ATPG, MBIST, Repair, Functional, DC, and HSIO
- Own NPI silicon bring-up for structural tests — debug and root cause failures to closure
- Deploy and optimize test programs at OSATs for yield, quality, reliability, and cost
- Develop custom test methods for product-specific requirements and contribute to wafer probe and final test hardware design
Requirements
- Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience
- 10+ years across ATPG, ATE test development, and DFT timing
- Expert-level Tessent proficiency — TestKompress and MemoryBIST
- Deep knowledge of fault models: stuck-at, transition, path delay, cell-aware, and SDD
- ATE test program development and OSAT deployment experience
- SDC constraint development for DFT test modes; timing closure using Tempus
- Ability to use agentic AI flows to automate ATPG and ATE test workflows
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