Signal Integrity & Power Integrity Engineer

Own the signal-integrity and power-integrity engineering that keeps our AI accelerator running clean — across die, package, and board.

You'll model and sign off the high-speed interface channels and power-delivery networks that move data and power through the system, set the SI/PI budgets the design is built to, and partner closely with the package, PCB, physical-design, and architecture teams to meet them.

This is a deep-expertise, signoff-owning role at the intersection of high-speed design and power delivery: where the electrical realities of advanced-node, high-bandwidth silicon collide with aggressive performance targets, your analysis is what gives the team the confidence to tape out and build.

What will you do

• Own signal-integrity and power-integrity analysis and signoff for DensityAI’s AI platform across silicon, package, board, and system — high-speed interface channels, power delivery, and decoupling strategy

• Use and develop AI assisted tool flows to accelerate SI/PI modeling, extraction, and signoff timelines

What we're looking for

• Exceptional abilities across SI/PI analysis: link budgeting, channel modeling and S-parameter extraction, IBIS-AMI, IR-drop and power-delivery-network (PDN) analysis, and EM/thermal-aware signoff

• 5+ years of SI/PI experience on very high-performance designs at advanced technology nodes (7nm or better) and high-speed interfaces (PCIe, DDR/LPDDR, HBM, 112G+ SerDes, or equivalent)

• Hands-on with industry-standard tools (Ansys HFSS / SIwave / RedHawk, Cadence Sigrity / Clarity, Synopsys, Keysight ADS or equivalent) for extraction, EM, and PDN analysis

• Demonstrated ability to work closely with package, PCB, physical design, and architecture teams to set and sign off SI/PI budgets across die–package–board

• (Optional) 2.5D / 3D and multi-die packaging (CoWoS, EMIB, chiplets, HBM interfaces), jitter / equalization design, co-packaged optics, or post-silicon SI/PI correlation and lab validation