Physical Design Engineer

Own floorplan-to-signoff physical design for one or more blocks of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out.

Own floorplan-to-signoff physical design for one or more blocks of our AI accelerator silicon

Use and develop AI-assisted tool flows to accelerate physical design and signoff timelines

Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff)

8+ years of experience on very high performance designs at advanced technology nodes (7nm or better)

Hands-on with industry-standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent) and signoff (PrimeTime, Tempus, or equivalent)

Demonstrated ability to work closely with architects, RTL designers, EDA vendors, and foundries to design and sign off complex chips

(Optional) Multi-die packaging (CoWoS, 2.5D / 3D), thermal / IR / EM signoff, signal integrity, or DFT-aware physical design