DV Formal Verification

Own block- and SOC-level formal verification, debug, and proof convergence for our AI accelerator silicon.

Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out.

• Own block- and SOC-level formal verification, debug, and proof convergence for our AI accelerator silicon
• Use and develop AI-assisted tool flows — including AI agents for proof guidance — to accelerate convergence on complex designs

What we're looking for

• Exceptional abilities in formal verification: property authoring (SVA / PSL), proof strategies, and tool-flow ownership
• Master's + 8 years of experience in block- and full-chip formal verification on complex SOCs
• Demonstrated ability to debug proof failures and drive convergence in collaboration with RTL designers and architects
• Hands-on with industry-standard formal tools (Synopsys VC Formal, Cadence Jasper, or equivalent)
• (Optional) Security verification, processor verification, equivalence checking, or AMS / IP-flow exposure

Final offers depend on level, location, and skills relevant to the role.

Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.