Engineer, Defect Reduction & Yield Enhancement

• Defect control ownership: Own defect control across multiple semiconductor process flows; monitor SPC trends, run correlation/commonality analysis, and support timely corrective actions to prevent inline excursions.
• Excursion response support: Support defect excursion investigations, including data pull/analysis, containment documentation, and disposition support for discrepant material.
• Defect reduction execution: Support clear goals for yield-limiting defect types; execute initiatives using Pareto and yield kill ratio analysis; help build and maintain out-of-control action plans (OCAPs).
• Metrology tool support: Support defect inspection and SEM review tool performance (recipe robustness, matching checks, monitoring plans) across darkfield/brightfield Automated Optical Inspection (AOI) and SEM review platforms.
• Cross-functional problem solving: Collaborate with Integration, Process, Equipment, and Operations teams to plan and execute experiments, perform segmentation/spatial signature analysis, summarize results, and propose actionable process optimizations.
• Data analysis and reporting: Analyze defect and yield data using KLARITY ACE Defect or similar software; communicate findings through clear written updates and presentations.
• Best practices and knowledge sharing: Learn and apply best-known methods (BKMs), and share learnings with peers and technicians as part of project execution.

• B.S. or M.S. in Electrical Engineering, Electronics Engineering, Chemical Engineering, Materials Science, Device Physics, or related technical field.
• 2+ years of experience driving defect reduction and yield enhancement in CMOS/BiCMOS or bipolar technologies and semiconductor unit processes.
• Strong communication skills (written, verbal, presentation).
• Strong analytical/problem-solving skills; able to make decisions using data.
• Ability to drive projects to closure while managing shifting priorities.
• Statistical analysis experience (t-test, ANOVA) and familiarity with JMP (or similar statistical software).

• Experience with defect inspection and review tools (e.g., KLA/ONTO bright field, dark field, Automated SEM review or similar tool set).
• Experience analyzing defect-to-sort correlation, yield kill ratios, and spatial signatures using tools such as KLARITY ACE, KLARITY Defect, or PDF DataPower or similar analysis software.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.

of Commerce - Bureau of Industry and Security and/or the U.S.

of State - Directorate of Defense Trade Controls.

As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

This position qualifies for a discretionary performance-based bonus which is based on personal and company factors

This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

for the position includes 10 paid holidays per year, paid vacation starting at 136 hours per year for full-time employees (prorated for part-time employees), and paid sick time that exceeds the requirements of the Washington State Sick Leave law.