CPU Design Verification Principal Engineer

Role overview

Minimum qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 4+ years of relevant experience.
• Alternatively, a master's degree in a relevant field with 3+ years of relevant experience.
• Alternatively, a PhD in a relevant field with 2+ years of relevant experience.
• Experience in power management verification.
• Experience implementing assembly and C language embedded firmware.
• Experience with C/C++, scripting languages, Verilog, and SystemVerilog.
• Strong understanding of CPU and CPU-based SoC power-management features.
• Experience verifying clock gating, power gating, UPF, DVFS/DCVS, reliability, and throttling.

Roles and responsibilities

• Verify boot, reset, clock gating, power gating, voltage/frequency management, limits, and throttling.
• Develop comprehensive CPU verification test plans with design and verification teams.
• Execute test plans using simulation and formal verification methodologies.
• Write checkers and assertions and develop stimulus.
• Verify power intent using UPF methodologies.
• Collaborate with architects and software and SoC teams to validate system use cases.
• Enable verification on emulators and FPGA platforms with the emulation team.
• Debug and triage failures in simulation, emulation, and silicon.

Preferred requirements

• Good understanding of CPU architectures and CPU microarchitectures.
• In-depth knowledge of digital logic design, microprocessors, debug features, and DFT architecture.
• Experience with formal verification and assertions is advantageous.
• Knowledge of DFT and structural debug methodologies, including JTAG, IEEE 1500, MBIST, scan dump, or memory dump.

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