Substrate IC Package Layout Design Engineer

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

10+ years of experience in IC substrate layout design for high-performance processors or accelerators.

Extensive experience with large substrate packages (>50mm) and complex high-density layouts.

Proven experience with high-power (700W+) package designs and robust power delivery networks.

Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches).

Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWos.

Advanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification).

Deep understanding of SI/PI principles and how they apply to package-level design.

Strong analytical skills and ability to work effectively in a fast-paced, cross-functional team environment.

Etched believes in the Bitter Lesson . We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.