Design Verification Engineer - Interface IP

5+ years of design verification experience

You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.

You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.

You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.

You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.

Experience handling vendors and integration of IP/VIP’s

UVM/System Verilog

Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We have a growing presence in Austin and a core team in San Jose (Santana Row), and we greatly value engineering skills. We do not have strict boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.