Performance Characterization Engineer

Architect and implement the core data collection framework for hardware performance counters on a custom PCIe-based accelerator.

Develop a kernel driver module or user-space service for low-overhead tracing of accelerator activity.

Design and build a correlated timeline view visualizing CPU API calls, driver submissions, PCIe transfers, and accelerator execution units.

Create an analysis pass to detect and quantify memory access inefficiencies or PCIe bandwidth saturation while transacting on a PCIe-attached accelerator.

Strong proficiency in C/C++ and Python.

Deep understanding of computer architecture (CPU, GPU, accelerators), memory hierarchies (caches, DRAM), and interconnects (especially PCIe).

Proven experience in low-level performance analysis, profiling, and bottleneck identification on complex hardware systems (GPUs, CPUs, FPGAs, or custom ASICs).

Experience with performance analysis tools (e.g., NVIDIA Nsight, AMD uProf, Intel VTune, perf, Tracy, ETW).

Solid understanding of operating system internals (Linux preferred), including scheduling, memory management, and driver interaction.

Experience working close to hardware, potentially reading performance counters or interacting directly with device drivers.

Direct experience developing performance analysis or debugging tools.

Experience with ML accelerator architectures (GPUs, TPUs, etc.).

Experience with kernel-mode driver development (Linux or Windows).

Understanding of compiler internals, code generation, and optimization.

In-depth knowledge of the PCIe protocol and analysis tools (PCIe analyzers).

Experience with firmware or embedded systems development.

Experience with hardware description languages (Verilog, VHDL) or hardware verification.

Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.