STA Synthesis Engineer
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Key skills for this role
Role Overview
Role and Responsibilities
Roles and Responsibilities
· Complete ownership of timing constraint at image sensor full chip and sub system levels.
This includes:
o Timing constraint (Hierarchical, Flat) development and release for Synthesis/PD work
o Timing constraint validation using various EDA tools
o Analysis of pre-layout and post-layout timing reports and debug
o Incremental update of constraint as and when it is required
o Working with RTL, DFT and PD teams independently and driving in timing closure both at sub system and full chip level.
· RTL PPA analysis (physical and power aware) at sub system levels for power, performance, area trade-off.
This includes:
o Running relevant EDA tool and generate reports
o Analysing the reports
o Working with RTL, PD teams to improve the quality of RTL and Physical implementation
· Development of necessary scripts in TCL, Perl and/or Python for efficiency improvement
Key Skills for This Role
Full Job Posting
Qualifications
- B.Tech/B.E/M.Tech/M.E
- Skills and Qualifications
- Disclaimer
- Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
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About Samsung
Samsung is a global technology company specializing in consumer electronics, semiconductors, and digital solutions.
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