SOC Physical Design and STA Methodology Engineer

Role and Responsibilities

Roles and Responsibilities

Experience in SoC Physical Design with proven track record in flow and methodology development (not just block implementation)

• Expert in scripting for EDA automation: Python (preferred), Tcl, Perl, UNIX shell

• Deep hands-on experience with PnR and Signoff tools: Synopsys (Fusion Compiler, PrimeTime, ICV, Formality) and/or Cadence (Innovus, Genus, Voltus, Tempus)

• Developed production-grade PnR flows for partition and Chip Top level designs including power planning, placement, optimization, and routing

• Strong STA fundamentals: Constraints (SDC) development, timing debug, OCV/POCV derates, PVT corners, and ECO flows

• Experience in low power and multi-voltage designs: UPF, power gating, voltage islands

• Built automation utilities for PnR execution, signoff analysis, and ECO implementation

• Solid understanding of libraries, cell architectures, and technology files for optimization and ECO stages.

• Experience with AI-driven optimization tools (DSO.ai, Cerebrus)

• Advanced ECO tool expertise (Tweaker, PrimeClosure)

• Formal verification (LEC) methodology experience

• Hierarchical STA and chip-top integration experience

• DTCO and advanced node (3nm, 2nm) exposure

• Debug, enhance, and release PnR and STA signoff flows for multiple projects and process nodes

• Develop utilities and automation to improve PPA, runtime, and ease of use for design teams

• Support partition and full-chip design teams on complex convergence issues, timing closure, and DRC fixing

• Explore and deploy new EDA capabilities and PPA optimization recipes to production flows

• Document flows, create regression tests, and train design teams on methodology best practices