SerDes Validation Leader

Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems.

Own transceiver equalization tuning, including CTLE, FFE, and DFE tap optimization, to maximize eye margin and minimize bit error rates across cable, backplane, and board-level topologies.

Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links.

Use high-bandwidth oscilloscopes, BERTs, pattern generators, and protocol analyzers to validate link performance and isolate issues.

Collaborate closely with SI/PI engineers to correlate lab-measured link behavior with layout, simulation, and channel models.

Work with firmware teams to support real-time link monitoring, configuration control, and automated validation flows.

Develop and run script-based lab automation, including Python-based test, measurement, and characterization workflows.

Help define best practices for SerDes bring-up, tuning, debug, and validation across the company’s hardware platforms.

Proven hands-on experience bringing up and validating physical 56G, 112G, or 224G PAM4 links, or high-speed PCIe Gen5/Gen6 interfaces.

Deep practical understanding of SerDes implementation, configuration, equalization, and physical-layer debug.

Strong knowledge of how TX/RX equalization settings affect signal integrity, jitter profiles, eye margin, and BER.

Advanced proficiency with high-speed lab equipment, including BERTs, real-time or sampling oscilloscopes, pattern generators, and protocol analyzers.

Experience with automated, script-based testing and lab characterization, preferably using Python.

Ability to debug complex link issues across silicon, board, cable, backplane, firmware, and system-level interactions.

Strong collaboration skills and the ability to work closely with SI/PI, hardware, firmware, and systems teams in a fast-moving engineering environment.

Experience with 112G or 224G PAM4 links in data center, networking, switch, accelerator, or high-performance compute environments.

Familiarity with Ethernet, PCIe, CXL, or other high-speed protocols.

Experience working with SerDes IP from major commercial IP providers or custom in-house SerDes teams.

Exposure to channel modeling, compliance testing, and production validation flows.

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