We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
What we need
We are looking for a Principal AMS Engineer to help architect, design, integrate, and validate the high-speed analog and mixed-signal technologies at the core of our products.
This is a highly technical, hands-on role spanning AMS/PHY architecture, circuit design, SoC integration, high-speed interfaces, clocking, power, package and board interaction, and silicon validation. You will work across the full development lifecycle—from early architecture and IP definition through implementation, tapeout, bring-up, and mass production.
The right person is comfortable operating beyond an individual circuit block. You understand how PHY, analog, digital, package, PCB, power, timing, and system-level considerations interact and can drive solutions across those boundaries.
Key Responsibilities
Architect and develop analog and mixed-signal circuits and subsystems for next-generation high-speed interfaces and SoCs.
Lead architecture and integration of high-speed PHY technologies, including die-to-die, UCIe-class interfaces, DDR, HBM, and related SerDes/PHY functions.
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Guide development of critical AMS functions including clocking, reference circuits, DLL/PLL-related functions, voltage monitoring, calibration, data-path circuitry, and other custom analog IP.
Drive chip/package/PCB co-design for high-speed signal and power integrity.
Own AMS for PHY integration into complex SoCs, including interface definition, floorplanning, clocking, timing, power intent, IO, and physical implementation considerations.
Partner closely with digital design, verification, physical design, package, systems, and software teams to resolve cross-domain design issues.
Develop and improve methodologies for signal integrity, power integrity, timing, low-power design, and system-level analysis.
Define requirements and evaluate internal and third-party analog, PHY, and interface IP.
Provide technical leadership for engagement with external IP, design-service, and technology partners.
Drive designs from pre-silicon architecture and verification through tapeout, bring-up, characterization, post-silicon validation, and production.
Diagnose complex performance and integration issues across silicon, package, board, and system boundaries.
Provide technical leadership, design reviews, mentoring, and architectural guidance across the engineering organization.
Help establish the design flows, standards, and infrastructure needed to build a world-class AMS capability from the ground up.
Required Skills and Qualifications
Master’s degree or Ph.D. in Electrical Engineering, Electronics Engineering, Microelectronics, or a related field, or equivalent practical experience.
Deep experience in analog and mixed-signal IC design and implementation.
Strong background in high-speed PHY architecture and design, such as DDR, HBM, die-to-die, UCIe, SerDes, MIPI, or similar interfaces.
Experience developing and integrating analog IP such as PLLs/DLLs, clocking circuits, voltage/reference circuits, ADCs/DACs, LDOs, IO, or related mixed-signal functions.
Strong understanding of SoC integration, including clocking, timing/STA, low-power design, UPF, IO integration, physical design interaction, and floorplanning.
Experience with high-speed signal integrity and power integrity across chip, package, and PCB.
Demonstrated ability to take complex silicon designs from architecture through tapeout and post-silicon validation.
Experience working closely with package, board, digital, verification, physical-design, and system engineering teams.
Strong technical judgment and the ability to independently drive ambiguous, cross-functional engineering problems.
Ability to influence architecture and technical direction without relying on organizational authority.
Desired Skills
Direct experience with UCIe or proprietary die-to-die interfaces.
Experience with advanced packaging, chiplets, or multi-die systems.
Experience developing complete PHY subsystems from architecture through silicon validation.
Background in IO/ESD and latch-up design and qualification.
Experience with analog timing characterization and design-flow/CAD infrastructure.
Experience managing or technically leading third-party IP and design-service vendors.
Experience building new design teams, flows, or technical capabilities from the ground up.
Prior technical leadership or mentoring experience across AMS, PHY, DV, or SoC integration teams.
Compensation
Competitive compensation aligned with Taiwan senior engineering roles. Exact compensation will vary based on experience and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
About Delos Data
Software & SaaS50 employeesFounded 2025
AI interconnect company building server hardware and software for hyperscalers, AI infrastructure builders, and enterprises scaling inference.
