Senior Technical Lead - Silicon Platform Validation, Python (134207)

Validate emulation models through sanity tests, boot tests, and golden-reference comparisons against RTL simulation

Ensure functional equivalence between RTL simulation and emulation by running correlation test suites

Debug and resolve model mismatches (simulation vs. emulation) due to synthesis artifacts, X-state handling, timing differences, or initialization issues

Validate memory models, I/O interfaces, and transactor/synthesizable BFM integration

Perform coverage analysis on emulation models and track model quality metrics

Maintain a regression suite for build-level validation (smoke tests, connectivity checks)

Develop and maintain automated build pipelines (CI/CD) for nightly/weekly emulation model builds

Create scripts and tools for build monitoring, error triage, capacity tracking , and build status reporting

Maintain version-controlled build configurations , design collateral, and release notes

Manage compute farm resources (LSF/SGE/Slurm) and optimize job scheduling for emulation builds

Track and manage platform licenses and capacity allocation across projects

Develop dashboards and metrics for build health, turnaround time, and platform utilization

Partner with RTL design teams on design readiness, coding guidelines, and synthesizability best practices for emulation

Work with verification/validation teams to integrate transactors, probes, and debug infrastructure into emulation models

Collaborate with firmware/software teams to deliver validated models for early SW development and hardware-software co-validation

Coordinate with EDA vendor support (Cadence, Synopsys) for tool issues, feature requests, and platform upgrades

Support silicon bring-up teams with emulation-correlated debug and pre-silicon regression data

Participate in project planning to communicate build schedules, risks, and dependencies

xeCompiler, xeDesignOptimizer, multi-domain clocking, ICE/SCE modes, speed optimization

FPGA-based prototyping, partitioning, multi-FPGA mapping, pin multiplexing, timing closure

zFAST/zTOP compile, design partitioning, ZCUI, transactor integration, ZeBu Server