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successfactors

Senior Technical Architect - Memory layout Design (129051)

HCLTech: Supercharging Progress | AI, Cloud and Engineering
IND
Full-time
Senior · 8+ years experience
Onsite
Discovered 3 weeks ago
Cadence VirtuosoCalibreAssuraDRCLVSPERL
Free

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Job Summary

We are seeking a highly experienced Memory Layout Architect with 8-12 years of experience to lead and innovate in the design of cutting-edge memory solutions for advanced integrated circuits (ICs). You will be a visionary leader who sets the technical direction for memory layout, pushing the boundaries of performance, power efficiency, and area optimization for next-generation products.

Responsibilities

  • Lead and define the overall memory layout strategy for complex IC projects.
  • Architect and design high-performance, high-density memory blocks, including:
  • Leading-edge SRAM and DRAM architectures
  • Specialty memory solutions (e.g., eMRAM)
  • Collaborate with design, logic, verification, and architecture teams to define memory specifications and ensure seamless integration.
  • Mentor and guide junior engineers, fostering a culture of technical excellence.
  • Stay at the forefront of memory design trends and technologies, actively researching and evaluating emerging solutions.

Skill Requirements

  • Develop and implement innovative layout techniques for ultra-low power, high-speed memory designs for advanced technology nodes (e.g., sub-7nm FinFET, GAAFET).
  • Champion Design for Manufacturability (DFM) and Design for Yield (DFY) principles across the entire memory design flow.
  • Oversee comprehensive physical verification using industry-leading tools (DRC, LVS, Calibre) and establish robust verification methodologies.
  • Drive automation efforts through scripting (PERL, Shell, TCL, Skill) to optimize layout tasks and improve design efficiency.
  • Manage and prioritize multiple complex memory design projects, meeting aggressive deadlines while maintaining the highest quality standards.

Qualifications

  • Master's degree in Electrical Engineering, Computer Engineering, or a related field (preferred)
  • 8-12 years of experience in leading memory layout design for advanced ICs
  • Proven track record of successfully designing and implementing high-performance memory solutions
  • Deep understanding of memory architectures, sub-blocks, functionalities, and emerging memory technologies
  • Expertise in memory layout tools like Cadence Virtuoso, Calibre, Assura, and familiarity with advanced place and route techniques
  • Extensive experience with low-power, high-performance memory design across multiple technology nodes
  • In-depth knowledge of DFM and DFY principles with a proven ability to implement them effectively
  • Exceptional leadership, communication, and teamwork skills
  • Ability to manage and mentor junior engineers
  • Strong analytical and problem-solving skills
  • Demonstrated ability to manage multiple projects, prioritize tasks, and meet deadline

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