Senior RTL Design Engineer (133943)

Candidates with 2 to 5 years experience is mandatory

Experience in RTL coding using Verilog/SV

Experience in design using Xilinx or Altera devices

Experience in using Vivado or Quartus

Experience in supporting lab debug

Good understanding of FPGA debugging techniques

2 to 5 years experience in front end design

Experience in CDC/Linting/Tool Flow

Experience with ASIC/SoC development flow including synthesis/Timing Constraints development is preferred

Experience in RTL Synthesis

Scripting experience is preferable