Senior Design Verification Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.

Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALinkTM semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.

Discover more at www.asteralabs.com.

As a Senior Design Verification Engineer, you will help build and validate complex connectivity silicon that enables the next generation of AI infrastructure.

You will develop scalable verification environments, integrate UVM and C/C++ workflows, and partner closely with RTL designers to identify and resolve issues across simulation, co-simulation, and emulation.

This is an opportunity to contribute across the verification lifecycle at a hyper-growth connectivity company.

Your work will help deliver reliable, high-bandwidth products that connect CPUs, GPUs, memory, storage, and networking devices in rack-scale AI systems.

• Verification Architecture and Planning
• Build and maintain UVM-based verification environments using SystemVerilog and C/C++ integration through DPI/PLI.
• Translate design specifications into verification plans, test strategies, and reusable test sequences.
• Develop VIP abstraction layers that simplify and scale verification across projects and platforms.
• Stimulus, Assertions, and Coverage