Digital Design Manager

Drive scan insertion, ATPG, compression, MBIST, LBIST, JTAG/IJTAG, and high-speed SerDes BIST requirements.

Establish coverage targets and review ATPG results, pattern quality, test time, and ATE cost.

Support tape-out, wafer sort, packaged-device test, silicon bring-up, characterization, and production ramp.

Collaborate with product, manufacturing, assembly, and test engineering on yield learning, failure analysis, and root-cause resolution.

Develop pre-bond, post-bond, and package-level test approaches for known-good-die screening and advanced packaging.

Improve diagnostic capabilities for silicon, package, and system-level issues.

Mentor DFT engineers and coordinate execution across product development milestones.

Partner with OSATs, ATE vendors, packaging partners, and internal stakeholders to resolve technical issues and maintain schedules.

Communicate risks, trade-offs, and recommendations clearly to cross-functional teams.

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.

10-15 years of experience in Digital Design engineering or related semiconductor design and test work.

Hands-on experience with scan, ATPG, compression, MBIST, LBIST, JTAG, and/or IJTAG methodologies.

Understanding of the ASIC design flow from RTL through GDS and DFT signoff.

with DFT EDA tools such as Synopsys DFT Compiler, TetraMAX, DFTMAX, Siemens Tessent, or equivalent.

Understanding of high-speed signal conditioning, SerDes physical-layer behavior, signal integrity, die-to-die connectivity, or advanced packaging test requirements.

Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.

with 2.5D or 3D integration, silicon interposers, TSVs, hybrid bonding, micro-bumps, chiplets, or known-good-die strategies.

Knowledge of IEEE 1838, IEEE 1149.1, IEEE 1687, and relevant JEDEC standards for multi-die testing.

with PCIe, Ethernet, UALink, and high-speed SerDes physical-layer validation or test.

Familiarity with ATE platforms, wafer probe, OSAT engagement, production test economics, and yield analysis.

range is CAD $198,000 to CAD $220,000 depending on experience, level, and business need.

This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.