Principal Advanced Packaging Engineer

About the Role

Responsibilities

• Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.
• Define and optimize wafer-level, panel-level, or die-level packaging process flows.
• Drive EIC-to-PIC integration and broader optical device integration efforts.
• Select and qualify packaging materials for advanced packaging.
• Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.
• Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages.
• Develop and maintain packaging PDKs and design rules for NPO and CPO products.
• Basic Qualifications:
• B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
• 8+ years of experience in semiconductor or advanced packaging engineering, with demonstrated technical leadership.
• Deep expertise in advanced packaging processes, including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and overmold across wafer-, panel-, and die-level flows.
• Experience with silicon photonics chip packaging and EIC/PIC integration.
• Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants.