Senior Analog / Mixed-Signal IC Design Engineer

Responsibilities:

• Design and develop analog and mixed-signal circuit blocks, including:
• Data converters (ADC/DAC)
• Amplifiers (LNA, TIA, op-amps)
• Bandgap references, biasing circuits, and regulators
• Define system architecture and drive trade-offs across noise, linearity, power, area, and bandwidth.
• Perform transistor-level design, simulation, and optimization using industry-standard tools.
• Develop behavioral models (Verilog-A / SystemVerilog RNM) for system-level verification and architectural exploration.
• Work closely with layout to ensure performance through parasitic-aware design and careful floorplanning.
• Run post-layout simulations and sign-off analyses (PVT, Monte Carlo, corner analysis).
• Collaborate with digital and verification teams for robust mixed-signal integration.
• Drive/manage silicon bring-up, debug, and lab characterization.
• Drive clear design documentation and participate in design reviews.
• Take ownership of deliverables and drive work to completion, including under tight timelines.
• Contribute across disciplines as needed, including outside primary specialization.
• Maintain organized workflows to manage simulations, design iterations, and analysis results
• Experience/Qualifications:
• MS or PhD in Electrical Engineering or related field.
• Strong fundamentals in analog circuit design and device physics.
• Proven experience designing and taping out analog or mixed-signal ICs.
• Expertise in CMOS or SiGe design across one or more process nodes.
• Proficiency with SPICE-based simulation tools (e.g., Spectre, HSPICE).
• Deep understanding of noise, mismatch, stability, and nonlinearity.
• Ability to design from first principles and solve complex circuit problems creatively.
• Strong organizational skills to manage large design spaces (corners, Monte Carlo, trade-offs).
• Demonstrated ownership mindset with a focus on delivering high-quality result.
• Preferred Qualifications:
• Experience with data converters, RF/analog front-ends, or high-speed interfaces.
• Experience with both mature and advanced process nodes (FinFET or beyond) a plus.
• Hands-on experience with silicon validation and lab debugging.
• Experience contributing across full chip development cycles.
• Experience with Cadence Virtuoso design environment.
• Hands-on experience with layout, tapeout, and bench validation.
• Familiarity with SystemVerilog RNM and/or Verilog-A modeling.
• What We Value
• First-principles thinking and strong engineering judgment.
• Ability to navigate complex trade-offs across performance, power, and area.
• Ownership from architecture through silicon validation.
• Clear and effective communication in cross-functional teams.
• Intellectual curiosity and a drive to continuously learn new tools, domains, and techniques.
• Flexibility to contribute beyond core responsibilities in a fast-paced environment.
• Strong organizational discipline when working across many design iterations.
• Receptiveness to feedback and commitment to continuous improvement.
• Reliability and accountability in meeting commitments.
• Willingness to go the extra mile to meet critical milestones
• PsiQuantum provides equal employment opportunity for all applicants and employees. PsiQuantum does not unlawfully discriminate on the basis of race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domestic partner status, sexual orientation, genetic information, or any other basis protected by applicable laws.
• Note: PsiQuantum will only reach out to you using an official PsiQuantum email address and will never ask you for bank account information as part of the interview process. Please report any suspicious activity to recruiting@psiquantum.com.
• We are not accepting unsolicited resumes from employment agencies.
• Base pay is one part of the total compensation package. Full-time roles are eligible for equity and benefits. Our compensation ranges reflect the cost of labor across multiple U.S. geographic markets, and we pay based on defined geographic zones. This position may be filled within one of the following U.S. geographic zones, each with its own salary range.
• Actual compensation may vary outside of these ranges and is dependent on various factors including, but not limited to, a candidate's qualifications, relevant education and training, competencies, experience, geographic location, business needs, and internal equity. Your recruiter can share more details about the salary range applicable to your location during the hiring process.
• Zone 1 - Bay Area and NYC
• Zone 2 - Examples include Los Angeles and Washington DC
• Zone 3 - Examples include Austin, Chicago, and Sacramento
• Zone 4 - Examples include Nashville and Phoenix/Tempe and many remote locations
• This position includes the following benefits: competitive health coverage for you and your dependents, 401(k) with company match, equity grants, access to financial wellness tools and planning resources, wellness benefits, family support programs, life and disability insurance, paid leave programs, company-designated paid holidays, discretionary time off (DTO), and an end-of-year company shutdown. Some of these benefits have eligibility requirements and may vary based on location, role, or employment status. Many of these benefits are subsidized or fully paid for by the company.
• The estimated annual base salary range for this role is: