RTL Design Engineer

Description

Minimum Qualifications

• BS and a minimum of 10 years relevant industry experience

Preferred Qualifications

• Proven knowledge of RTL design, Verilog and SystemVerilog
• Deep knowledge of front-end tools (Verilog simulators, linters, CDC, RDC, LEQ, UPF)
• Low power design methodologies and techniques to reduce dynamic and static IC power
• ECO design flows and methodologies
• Proven understanding of mixed signal concepts and experience with analog circuit behavioral modeling
• Proven knowledge of synthesis, static timing and DFT
• Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques
• Knowledge of scripting languages (i.e. Perl, JSON and Python)
• Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code
• Digital signal processing fundamentals including signal processing concepts
• Strong communication and presentation skills