Principal Engineer Design

• As a Low Power Methodology engineer, you will work with the Power Management Architect for feasibility studies.
• Drive UPF methodology across frontend and backend teams for power intent and verification.
• The person will also be responsible for creating and maintaining workflows for early power estimation, incorporating EDA tools in the Infineon design flow used by all design teams.
• Work on low-power design methodology, define methods to derive UPF from higher-level abstractions, and power intent verification methods at the chip level
• Work with ASIC design flows and methodologies, including RTL, verification, synthesis, and static timing analysis (STA).
• Work with EDA vendors and tools team to define new power methodologies, automated UPF generation, and low power analysis.
• Partnering with design and verification teams to troubleshoot and fix UPF-related workflow challenges.
• Define and maintain workflows, including EDA tools for early power estimation
• 12+ years of relevant experience
• Familiar with low-power design implementation, including UPF/CPF, multi-voltage domains, and power gating.

with power intent definition, implementation, and verification flows.

• Strong understanding of ASIC design flows and IP design flows.
• Very good scripting and programming skills in Python
• Good scripting skills in TCL
• Familiar with power analysis and optimisation methods.
• Hands-on experience with low-power static checkers
• Hands-on with Power analysis, estimation and reduction tools like Power Artist, Prime-Power RTL or Joules.
• Additional skills in the following areas are a plus:
• UPF-based synthesis and implementation
• Experience with GitLab, SonarQube, PyTest, VSCode, Git, and Perforce
• Familiar with CI/CD pipelines and Software development methods. Familiar with object-oriented programming in Python, Power Software features for power optimisation, Voltage regulators, including Buck and Low Dropout