lever
PD - Principal, Physical Design
Eliyan
USA
Full-time
Senior · 8+ years experience
Onsite
Discovered 1 weeks ago
PVCTSFloorplanning
Free
Job Fit Check
Base Career helps you apply smarter for this job.
?%
Ready to ScanKey skills for this role
PVCTSFloorplanning
Key Skills for This Role
PVCTSFloorplanning
Full Job Posting
- Architecture and packaging driven floorplanning and integration so physical partitions match system and package constraints
- Well defined boundaries with lego style pin alignment and consistent interface placement across chip and blocks
- Feedthrough, repeater and bus planning with early reservation of routing corridors, layers, and resources for cross block connectivity.
- Define clocking architecture methodology selecting spine and rib, H tree, or mesh to optimize power, skew, latency, and robustness.
- Establish CTS methodology including skew and latency targets, buffer and ICG strategy, NDR and shielding rules for critical clock routes.
- Define skew groups and balancing strategy across library corners, ensuring consistent behavior under MMMC variations and derates.
- Drive clock constraint quality across hierarchy with clean chip to block and block to chip handoff for signoff readiness.
- Define DRC aware power grid architecture including rings, straps, and mesh, matching metal resistivity assumptions to IR drop targets and EM limits.
- Ensure careful planning around analog routing with keepouts, shielding, spacing, and grid topology choices that preserve sensitive nets and meet DRC.
- Drive lego aligned power mesh alignment across top level, subsystem, and block level with consistent strap pitch, via patterns, and clean connectivity.
- Lead early and signoff EM and IR analysis, identify hotspots, and implement grid reinforcement and via optimization without routing or congestion penalties.
- Align power planning with floorplan and package constraints including bump map, current demand, and entry points to minimize noise and IR drop.
- 8 to 12 years ASIC physical design experience owning floorplanning integration clocking and power planning from early feasibility through signoff and tapeout on complex SoCs
- Expert in architecture and package driven hierarchy planning with lego aligned boundaries pin strategy feedthrough repeater bus planning plus CTS methodologies including spine rib H tree or mesh
- Strong EM IR PV and STA awareness with MMMC and library corner skew group balancing advanced node exposure TSMC 3nm 2nm or Samsung 2nm and functional ECO execution experience
Apply for this job in 1 click
Skip the repetitive application forms
Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.
Trusted by over 500,000 job seekers on Base Career
More from this employer
More jobs at Eliyan
Signal and Power Integrity Engineer
, USA
Discovered 1 weeks agoFull-time
Staff DFT Engineer
, USA
Discovered 1 weeks agoFull-time
Digital Design Engineer (title will reflect experience)
, USA
Discovered 1 weeks agoFull-time
Digital - Principal Systems/DSP Engineer
, USA
Discovered 1 weeks agoFull-time
Staff AMS CAD Engineer
, USA
Discovered 1 weeks agoFull-time
PD - IP Lead – Sr Staff, Physical Design
San Francisco, USA
Discovered 1 weeks agoFull-time
DV - Director of Design Verification
, USA
Discovered 1 weeks agoFull-time
Digital - SerDes Digital Design Lead
, USA
Discovered 1 weeks agoFull-time