lever
Digital Design Engineer (title will reflect experience)
Eliyan
USA
Full-time
Senior · 5+ years experience
Onsite
Discovered 1 weeks ago
SystemVerilogEthernet PMA/PCSUPF/CPFLINT/CDC
Free
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SystemVerilogEthernet PMA/PCSUPF/CPF
Key Skills for This Role
SystemVerilogEthernet PMA/PCSUPF/CPFLINT/CDC
Full Job Posting
- Design, develop and/or integrate Ethernet PCS/PMA IPs for various data rates (100/200/400/800G)
- Develop micro-architecture specifications and implement digital designs using SystemVerilog
- Ensure compliance with Ethernet standards (IEEE 802.3)
- Optimize designs for power, area, and performance
- Collaborate with verification engineers for IP verification
- Work closely with physical design team for physical implementation
- Participate in design reviews and ensure design quality
- Develop and maintain all IP design collaterals that include documentation, RTL, SDC constraints, power intent definition (UPF/CPF), LINT/CDC rule files and waivers
- Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
- Bachelors or Masters or Ph.D in Electrical Engineering and related fields, or equivalent
- 5+ years of experience in high-speed digital design (preferably in retimer, gearbox, Ethernet PMA/PCS logic)
- Strong expertise in RTL and Assertion coding with SystemVerilog
- Proficiency in taking RTL through synthesis and produce a PPA optimized frontend netlist
- Knowledge of Ethernet 802.3 standards’ clauses related to 100G/200G/400G/800G, Auto-Negotiation and Link Training
- Strong bias for innovations across all aspects of digital design including automation of mundane activities and methods for quality improvement
- Experience integrating 3rd party mixed signal IPs
- Proven track record of being part of a start-up like environment
- Knowledge of DRAM Controllers/PHYs and HBM Memory a plus
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