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As a Physical Design intern for Etched this fall , you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions.
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
As a Physical Design intern for Etched this fall , you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions.
Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
Familiarity with high-speed digital logic
Exposure to ASIC or SoC design concepts
Familiarity with SystemVerilog, UVM, or Python
Familiarity with verification work and writing test benches
Familiarity with physical design flows and tooling
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Are able to learn quickly about transformers and other aspects of modern artificial intelligence
12-week paid internship (August - December 2026)
Generous housing support for those relocating
Daily lunch and dinner in our office
Based at our office in San Jose, CA
Direct mentorship from industry leaders and world-class engineers
Opportunity to work on one of the most important problems of our time
For any questions, contact internships@etched.com
Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Private semiconductor startup building AI inference chips, racks, and software for frontier-model customers.
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