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We’re looking for a hands-on process and materials engineer to own wafer level molding and underfill processes, material qualification, and assembly integration across development and manufacturing.
Seeking an experienced engineer to lead wafer level mold and underfill process development for advanced semiconductor packages (fan-out wafer level packaging, 2.5D/3D, chiplet).
This role spans
mold compound and underfill material selection and qualification, wafer level molding and encapsulation processes, underfill dispense and cure, reliability, failure analysis, and cross-functional support through package and system productization.
molding, and mold underfill (MUF) for fan-out and advanced heterogeneous packages.
filler content, CTE, modulus, Tg, viscosity, and moisture uptake to meet thermo-mechanical and
reliability requirements.
and void optimization, and cure profile development for high-density flip chip and chiplet
assemblies.
mold flash, and filler settling; define process windows and controls to ensure repeatable yield
across wafer and panel formats.
dispense and cure equipment requirements, and manage process transfers into production.
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adhesion, CTE, modulus) and correlate material behavior to process outcomes and package
reliability.
interconnects with various underfills and predict warpage with various mold compouds.
cycling.
robust package performance from concept through high-volume production.
packages including fan-out wafer level packaging (FOWLP), 2.5D, and chiplet architectures.
systems, filler particle size and loading, cure chemistry, and how material properties drive
thermo-mechanical package behavior.
characterization, bleed-out control, and cure process optimization including staged and snap
cure profiles.
CTE mismatch, warpage evolution through cure and reflow, delamination driving forces, and
material-induced reliability risks.
SEM/EDS, CSAM, TGA, DSC, and DMA for material characterization and thermal cycling reliability
evaluation.
underfill processes into production, including equipment setup and process control plans.
manufacturing environments, including DOE-driven process optimization.
encapsulants and low-modulus underfills.
2.5D interposers, 3D stacking, chiplet assemblies, and CoWoS-like structures where material
interactions and warpage are critical constraints.
adhesives and underfills for photonics, high-filler, low-CTE mold compounds for 2.5D interposer
assemblies.
material thermal conductivity, warpage stability, and coefficient of thermal expansion are tightly
constrained.
prediction, delamination risk assessment, and material property sensitivity analysis for mold and
underfill optimization.
level molded wafer).
Private semiconductor startup building photonically integrated computers and photonic interconnects for AI inference and data-center systems.
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Senior Level
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