Packaging Engineer- Bump Interconnect

• Strong experience in bump interconnect processes including ubump (Cu pillar, micro-bump) and

C4 bumping for semiconductor devices.

• Deep understanding of bumping metallurgy including UBM stacks, solder alloy systems (SnAg),

intermetallic compound (IMC) formation and growth kinetics, and their impact on joint reliability.

• Experience with RDL plating processes including Cu electroplating, photoresist patterning, seed

layer deposition, and associated design rules for line/space, via geometry, and pad stack.

• Understanding of thermo-mechanical behavior in bump interconnect assemblies including CTE

mismatch, warpage, solder joint fatigue, and IMC-driven reliability risks for both ubump and C4

configurations.

• Hands-on experience with failure analysis and reliability testing (cross-sections, SEM, CSAM,

thermal cycling).

• Ability to work with OSATs and suppliers to develop and transfer assembly processes into

production.

• Strong problem-solving skills with ability to debug yield and reliability issues in manufacturing

environments.

• Experience with III-V packaging, photonics packaging, and precision chip attach.
• Experience with advanced packaging technologies including 2.5D interposers, 3D stacking,

chiplets, and CoWoS-like architectures.

• Familiarity with fine-pitch micro-bump and hybrid bonding approaches.
• Experience integrating high-power or high-TDP devices with tight warpage and thermal

constraints.

• Exposure to thermo-mechanical modeling or collaboration with simulation teams for warpage

and reliability prediction.

• Understanding of system-level interactions (warpage, second-level interconnect reliability).
• Deep expertise in bump metallurgy fundamentals including UBM stack design (Ti/Cu, etc.), solder

alloy selection, wetting behavior, and the influence of plating chemistry and process conditions

on bump morphology and composition.

• Fundamental knowledge of intermetallic compound (IMC) formation, growth kinetics, and phase

behavior in Cu/Sn, Ni/Sn, and Au/Sn systems; understanding of how IMC thickness, morphology,

and composition affect joint strength, electromigration resistance, and long-term reliability.

Industry experience in semiconductor packaging with strong emphasis on bump interconnect

processes, RDL development, and productization.