MTS - DPG Layout

• 15 + year experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
• Should have hands on experience of Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Should have hands on experience in handling various memories like DRAM, SRAM, CAM, OTP etc
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.
• Ability to understand design constraints and implement high-quality layouts.
• Excellent command and problem-solving skills in over Physical layout verification.
• Should have experience in leading multiple project and Tape-out.
• Experience in scripting and automation.
• Excellent verbal and written communication skills.
• Education - BE or MTech in Electronic/VLSI Engineering.

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