Principal Foundry Interface Design Engineer, HBM

Foundry Interface and Technology Alignment

Act as the primary technical interface between foundry partners and Micron design organizations.

Drive closure of design-process gaps through collaborative engagement with foundry process teams.

Influence foundry roadmaps related to TSV, BEOL, reliability, and design enablement.

Define technology requirements for future HBM and custom memory products.

Perform HSPICE simulations for technology evaluation and design optimization.

Evaluate compact models, PDK SPICE models, and process corners.

Conduct pre-layout and post-layout circuit analysis.

Support BEOL optimization and routing studies through simulation.

Develop methodologies for evaluating design sensitivity to process variations.

Plan and execute technology evaluation test chips.

Define process monitor structures and benchmark vehicles.

Analyze post-silicon data and correlate results with simulations.

Collaborate with product engineering and foundry/Fab teams on silicon learning and technology qualification.

Evaluate foundry PDKs and IP collateral.

Support design teams by providing technology guidelines and best-known methods.

Drive creation of design recommendations, analog guidelines, and digital PPA evaluation methodologies.

Collaborate with CAD teams on flow enablement and validation.

Identify and implement AI-enabled workflows, automation opportunities, and knowledge-management practices to improve engineering productivity, decision quality, and execution efficiency across DTCO, foundry interface, PDK evaluation, and design enablement activities.

BS, MS, or PhD or equivalent experience in Electrical Engineering, Computer Engineering, or related field.

6+ years of semiconductor industry experience, solid grasp of advanced semiconductor technology development.

Strong understanding of advanced CMOS technology nodes, FinFET devices, and process integration.

Hands-on experience with: HSPICE simulations, Device characterization, Standard cell benchmarking, PPA analysis, Parasitic extraction and physical verification

Experience in driving AI-enabled engineering practices and automation to improve the efficiency of DTCO analysis, foundry collateral evaluation, PDK enablement, benchmarking, and knowledge sharing across design teams.

Experience working directly with leading foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries.

Experience with memory products including DRAM, HBM, or SRAM.

Knowledge of: TSV technologies, Advanced packaging, Reliability modeling and aging simulations, Advanced BEOL technologies, PDK development and validation

Ability to utilize AI tools to summarize, analyze, and extract insights from: PDK documentation, Design Rule Manuals (DRM), Reliability reports, Foundry collateral, Silicon characterization data

Experience leading technology pathfinding and node selection activities.

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The US base salary range that Micron Technology estimates it could pay for this full-time position is:

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