Kernel Driver Software Engineer

Develop and optimize kernel-mode drivers for new ML accelerators.

Implement and optimize memory management, including kernel memory mapping and IOMMU configurations, for high-bandwidth data transfers.

Debug and resolve complex driver-related issues impacting ML workload performance.

Develop performance benchmarks and profiling tools to analyze driver performance.

Integrate driver support for advanced features like hardware virtualization and security, including SR-IOV and VFIO.

Optimizing PCIe communication between the host and PCIe devices, using advanced equipment like PCIe analyzers.

Implement and debug power management features for PCIe devices.

Integrating ML accelerators into containerized and virtualized environments.

Implementing and optimizing para-virtualization techniques for PCIe devices.

Configure and optimize page tables for efficient memory access from the ML accelerator.

Participate in hardware-software co-design reviews across teams to optimize performance and power efficiency.

Candidates with experience in developing and debugging kernel-mode drivers for GPU or other accelerator devices.

Candidates with a strong understanding of hardware/software interactions.

Candidates with experience in optimizing driver performance for demanding workloads.

Candidates with experience in ML workloads.

Candidates who have debugged complex hardware and software interactions, especially in virtualized environments.

Candidates with experience in implementing and optimizing SR-IOV and VFIO.

Candidates with in-depth knowledge of kernel memory mapping, page tables, and IOMMU.

Candidates with experience in hardware-software co-design projects.

Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.