IO/Analog Layout Engineer

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As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.

When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.

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People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.

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Our technology starts with you.

To develop advanced parallel standard IOs like I2C, SPI and GPIO layout design in differentiated sub-micron technology with specific requirements like different supply and pad voltages.

Having experience on designs like SLIMBUS, LVDS & USB2.0 and on differentiated sub-micron technology would be a plus Major responsibilities / skills include Developing layouts for IO suitable for the required specifications / customer needs Experience in layout of IO/analog blocks as well as floor planning activity.

Proficient in EDA tools used for layout design (e.g.

Virtuoso/OA for layout design – L/XL/GXL, Calibre for DRC/LVS/DFM, StarRC/QRC for Extraction, tools for Electro-migration and IR Drop analysis) Good understanding of Design Rule Manual and Design Rules Good understanding of IO, Analog Layout fundamentals (e.g.

ESD, Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)

in layout of IO/analog blocks as well as floor planning activity.

Good understanding of electrical schematics and link between layout and resulting electrical performances and manufacturability.