IC Package Engineer

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.

We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive experience with advanced packaging technologies such as CoWoS, large-scale BGA designs, and package warpage mitigation strategies. You will play a key role in ensuring the mechanical and electrical integrity of packages that power the next generation of AI hardware.

Own the end-to-end package design process, including substrate layout and IC package design, while collaborating with internal teams and external vendors to deliver optimized, manufacturable solutions

Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating stiffeners as needed

Expertise in large-scale BGA design, including experience with packages exceeding 4000-ball arrays, ball pitch optimization, routing, and power/ground plane design

Conduct mechanical and warpage analysis to address package warpage and coplanarity requirements across varying package sizes, collaborating with mechanical teams for simulation and testing to minimize thermal and mechanical stress

Perform design validation by assessing package layouts against electrical and mechanical constraints, providing design reviews and guidance on substrate and interconnect solutions, while archiving DFM-related learning for continuous improvement opportunities