Formal Verification - DV

5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon.

Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.

Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.

Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.

Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.

Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports.

Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams.

You thrive in a fast-paced startup environment and can take ownership of ambiguous, high-impact verification problems.

Formal verification of systolic arrays, DMA engines, NoCs, memory subsystems, arithmetic datapaths, PCIe, Ethernet, AXI/AMBA, CPU interfaces, or low-power controllers.

Protocol compliance checking, connectivity checking, register verification, datapath validation, reset verification, or deadlock/livelock analysis.

Vendor IP integration, encrypted or black-box IP verification, VIP configuration, and contract-based verification around subsystem boundaries.

Sequential LEC, floating-point or integer arithmetic proofs, cache coherency checks, interrupt handling, or memory-mapped IO verification.

Scripting in Python, TCL, Perl, or similar for automation, regression management, debug, and dashboarding.

Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.