greenhouse
Director of Buffer & Memory Subsystem Architecture
SK hynix America
CAN
Director · 8+ years experience
Discovered 1 weeks ago
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Role Overview
As the founding technical lead, this expert will spearhead the HW/SW co-design of next-generation HBF–xPU systems, translating complex AI workload traces into precise architectural policies for caching, prefetching, and data movement.
The role demands deep hands-on expertise in memory controllers and performance modeling to define interface contracts and optimize system-level efficiency across the hardware and software stack.
Key Skills for This Role
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Responsibilities:
- Serve as the founding technical lead of the HBF R&D team, owning HW/SW architecture decisions and technical alignment with headquarters and external partners.
- Lead HW/SW co-design by defining architecture, functional partitioning, and interface contracts across the HBF hardware and software stack.
- Drive HBF system optimization through memory architecture, performance modeling, and system-level implementation.
- Develop HBF system models and event-/trace-driven simulators for AI memory performance analysis.
- Analyze workload performance and optimize latency, bandwidth, and memory efficiency through architecture modeling.
- Validate architectural assumptions and provide data-driven insights for cross-functional architecture decisions.
- Define HBF Memory Architecture and Policies.
Qualifications:
- 8+ years of experience in Memory Controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, and DMA/Data Movement architectures, including the development of queueing, scheduling, and buffer management algorithms.
- Strong expertise in system performance analysis, including memory latency, bandwidth, locality, contention, and Workload characterization, with the ability to translate complex workload traces into architectural policies.
- Proven HW/SW co-design experience, including the ability to translate AI workload, compiler, runtime, and inference-engine behavior into memory hierarchy, data-movement, prefetch, scheduling, and programming-model requirements.
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