greenhouse

3D Stacked Logic Design Engineer

SK hynix America

CAN

Mid · 5+ years experience

Discovered 1 weeks ago

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Strengthen leadership in the DRAM-on-Logic era through advanced digital IP design for 3D-stacked DRAM.
Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
Co-design 3D-stacked DRAM Logic Dies with U.S.-based customers.
Improve competitiveness through close engagement with customers in the U.S.
Design high-speed digital IP for 3D-stacked DRAM peripheral circuits and DRAM DFT with U.S.-based customers, covering RTL design to implementation.
Conduct foundry verification of service-ready IPs and setting up infrastructure for the IP business.
Deliver services to ensure seamless IP integration in customer design environments.
Design digital logic blocks for 3D-stacked DRAM peripherals and Design-for-Test (DFT) features.
Establish close technical engagement with key U.S.-based customers to address immediate 3D-stacked DRAM requirements.
Establish close technical engagement with foundry partners (e.g., TSMC, Intel) to build digital IP for 3D-stacked DRAM.

Bachelor’s degree or higher in Electrical Engineering or a related discipline with 5+ years of relevant experience.
Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design.

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