DFT Intern

Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression

Experience with Tessent or similar DFT tooling

Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)

Exposure to DFT flow automation or regression infrastructure

Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet every single qualification.

12-week paid internship (June - August 2026)

Generous housing support for those relocating

Daily lunch and dinner in our office

Based at our office in San Jose, CA

Direct mentorship from industry leaders and world-class engineers

Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com .

Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.