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Design Verification Manager
Texas Instruments
Bengaluru, IND
Manager · 8–12 years experience
Discovered 2 weeks ago
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Responsibilities:
- End-to-End ownership of IP/subsystem/SOC DV/Post silicon debugs ownership right from spec definition till the post silicon verification and solving the customer issues. This includes:
- Technical:
- Actively collaborate with the architecture team during the specification definition phase.
- Define the verification strategy along with a plan to ensure 100% traceability between specifications and regression, including standard signoff metrics.
- Conduct IP, SubSystem, and SoC verification, covering both functional and firmware scenarios in RTL/PARTL and GLS/PAGLS modes.
- IP/SS/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.
- Own the DV environment, which includes defining and developing test benches, enhancing UVC integration, updating checkers and coverage monitors, and adapting the DV flow as needed for the project.
- Proficient in analog and mixed-signal (AMS) verification, clock domain crossing (CDC) digital verification, formal verification, and post-silicon verification.
- Work closely with cross-functional teams - including Architecture, RTL, PD, DFT, Systems, Analog, Firmware, and Application teams - to achieve verification goals for IP, subsystem, and SoC from specification definition through to post-silicon verification closure.
- Provide final SoC DV signoff based on regression results, coverage metrics, and DV to specification traceability using C and/or SV-UVM, while adhering to ISO 26262/ISO 21434 guidelines.
- Actively participate in customer reviews and certification processes (ISO 26262/ISO 21434).
Qualifications
- Minimum requirements:
- Education: Bachelor’s or Master’s degree in EE/EC/EI/CS, or related specializations.
- Experience: A minimum of 8-12 years in relevant fields.
- Preferred Skillset:
- Experience in C-based System-on-Chip (SoC) design verification (DV), with exposure to firmware verification and deep understanding of UVM/SystemVerilog, Specman, GLS/PAGLS/UPF based verification, post-silicon verification, etc.
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