Core Software Engineering

Build Reliable, High-Performance Systems for Engineering at Scale: Design the core frameworks and workflows that enable Etched’s engineers to iterate faster than anyone else in hardware. This includes building software that drives hybrid superclusters, with an extremely high compute-to-engineer ratio – your work will orchestrate thousands of machines to simulate, verify, and build chips continuously, with performance and correctness guaranteed.

Engineer World-Class Continuous Integration for Hardware: Invent and implement fault-tolerant, high-throughput CI pipelines for our entire backend – simulation, synthesis, CDC, and more. You’ll help build systems that surface correctness and performance regressions across nightly flows, and make high-assurance silicon development as continuous and automated as software deployment.

Scale Bare-Metal Superclusters and Hybrid Infrastructure: Work hands-on with on-prem systems to design compute infrastructure purpose-built for AI chip development. You’ll be orchestrating physical clusters across racks and clouds, thinking deeply about CPU/memory topology, EDA workloads, and how to saturate every core, all the time.

Design High-Quality Tools That Engineers Love Using: EDA workflows are stuck in the early 2000s – non-reproducible, slow, and hard to use. You’ll build from first principles: new interfaces, new dev workflows, and new execution engines that treat compute as cheap and time as sacred. Your tools will turn hours into minutes for the rest of our team.

Tools for Everything: Build a fully automated, correctness-first CI system that continuously runs performance regressions, CDC checks, simulations, and synthesis flows. Make chip verification as fast and seamless as shipping web code.

Massively Parallel Workload Scheduler: Design and deploy a dynamic scheduler for orchestrating compute-heavy workloads across thousands of on-prem and cloud cores. It should balance throughput, reliability, and fault tolerance while abstracting the underlying hardware complexity from users.

On-Demand, GPU-Backed Dev Environments: Create infrastructure that launches reproducible, zero-downtime interactive environments – backed by GPU nodes and hardened against flaky hardware. Developers should be able to spin up environments instantly, run massive workloads, and never worry about cluster volatility.

Scale-Aware Workload Migration: Prototype systems that intelligently migrate CI and simulation workloads across heterogeneous infrastructure, optimizing for performance and minimizing downtime—especially under variable hardware availability and cost constraints.

High-Fidelity Fault Simulation: Develop fault injection and synthetic testing frameworks that simulate hardware failures, degraded networking, and extreme load conditions – validating that our pipelines remain reliable under real-world stress.

Have Strong Systems Programming Skills: You’re fluent in languages like Go, Rust, or C++ and have familiarity with scripting as well.

Embrace Deep Technical Challenges: You’re not afraid to dive into kernel internals, debug tricky hardware-software interactions, or design low-latency pipelines from first principles.

Are Obsessed With Developer Productivity: You want to build tools that help great engineers move faster and with greater confidence.

Treat Infrastructure as Code: You believe great infrastructure is software – clean, testable, versioned, and designed for maintainability.

Designing and operating large-scale CI systems, build farms, or simulation clusters.

Architecting hybrid infrastructure across bare-metal and cloud providers.

Optimizing compute environments for performance-critical workloads, including memory-bound simulations and multi-node orchestration.

Working in environments where correctness, reproducibility, and performance are existential requirements.

Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.