ASIC Design Engineer

ASIC Verification using SystemVerilog

Experience in constrained-random verification is a strong plus

Experience with verification methodology like OVM/VMM/UVM

Perl/Tcl scripting is strongly preferred

Experience verifying networking protocols such as Ethernet is desirable

Strong problem solving and ASIC debugging skills

MSEE or BSEE is required with 5 plus years of experience.

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