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We have an exceptional opportunity for a Verification / Senior Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you’ll deliver fully verified, high-performance, and trusted systems.
In this exciting role you'll have end-to-end visibility across the entire stack, owning every aspect of verification and shaping how quality and reliability are built into our cutting-edge technology. You do not need a background in quantum computing! You will learn this along the way.
Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.
Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.
We have an exceptional opportunity for a Verification / Senior Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you’ll deliver fully verified, high-performance, and trusted systems.
In this exciting role you'll have end-to-end visibility across the entire stack, owning every aspect of verification and shaping how quality and reliability are built into our cutting-edge technology. You do not need a background in quantum computing! You will learn this along the way.
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Cambridge, GBR
Cambridge, GBR
Boston, USA
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Cambridge, GBR
Cambridge, GBR
Boston, USA
Cambridge, GBR
Cambridge, GBR
Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
Proven experience of testbench design with verification frameworks like UVM/OVM.
Knowledge of SystemVerilog assertion (SVA).
Exposure to different programming languages, such as C, C++ and Python.
A proactive person who can independently define the scope of work.
A collaborative person with excellent communication skills, who actively shares (and listens to) constructive feedback.
Ability to work effectively with ambiguity and changing requirements.
Experience debugging across RTL, simulation, and hardware
Formal verification experience.
A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme
Equity, so that our team can share in the long-term success of Riverlane
28 days annual leave, plus bank holidays and enhanced family leave
A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities
A learning environment that encourages individual, team and company growth and development, including a regular programme of learning events and training and conference budgets
Quantum computing company building real-time error-correction software and hardware for computer makers, governments, and research labs.
Visit company websiteJobs and hiring trendsGBP 60000-88000 yearly / year
Full-time
Senior
Hybrid
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