Summer 2027 Long Term Hardware Design Engineering Intern/Co-Op

12 Months: May 03, 2027 to April 21, 2028

16 Months: May 03, 2027 to August 18, 2028

WHAT YOU WILL BE DOING:

We are seeking a highly motivated Hardware Design engineering intern/co-op to join our team and work towards design, built, and delivery of AMD’s high-end Machine Intelligence products. In this role you will participate in one or more of (but not limited to) the below assignments –

Collaborate with Design Engineers on the physical design verification and physical implementation for some of our ASIC.

Work on Memory interface simulation work eg. GDDR7, HBM, UCIE.

Work on Discreate and Embedded hardware products and chip to chip interconnect.

You will actively participate in RTL design in Verilog.

Synthesis with timing driven placement and design for power (DFP).

Floor planning, Power distribution, Clock distribution, Block/Chip Place & Route, EM/IR analysis, Timing closure, Static Timing Analysis.

Some other tasks that we may assign you will include analysis of logical equivalent check, RTL clocking analysis, static power analysis, and design for test (DFT).

We will also train you to build test libraries and models by using advanced verification languages such as System Verilog, UVM and C++.

WHO WE ARE LOOKING FOR:

Currently enrolled in a Canada based University into a Bachelor's degree program majoring in Electrical engineering or Computer engineering or a related field.

If you have experience with any of the following technical skills (or related areas) and are enthusiastic about this role, we strongly encourage you to apply – Strong semiconductor device physics knowledge. Digital /Logic circuits and VLSI Verilog or VHDL hardware description languages Exposure to UVM methodologies Scripting languages (e.g. Python, Perl, TCL, Ruby), Shell / UNIX scripting, C/C++, MATLAB. Interest or experience in Machine Learning. ASIC design Knowledge of Ruby on Rails and MySQL Linux/Unix environment Physical design (PD) process Chip level design/integration activities and DFT