Design Verification Lead

THE ROLE: The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience in collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Verification of IP features : Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage: code-coverage, functional coverage, assertions to achieve 100% verification completeness Reviews, and feedback to design/architecture teams. PREFERRED EXPERIENCE: Years of experience 15+ Required. Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA) Expertise in code and functional coverage. Excellent Problem solving and debugging skills. Excellent Communication skills Strong digital design knowledge. Exposure to UPF based low power RTL verification. Prior experience in leading a team is desirable. Prior experience in PLL verification and Mixed signal verification methodology is highly desirable. Exposure to digital-analog co-simulations (cosims) is desirable. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics engineering/Electrical Engineering

Verification of IP features : Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations.

Create methodology-based (UVM) verification testbenches and components from scratch for various IP features.

Quality deliverables through regressions

Verification coverage: code-coverage, functional coverage, assertions to achieve 100% verification completeness

Reviews, and feedback to design/architecture teams.

Years of experience 15+ Required.

Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA)

Expertise in code and functional coverage.

Excellent Problem solving and debugging skills.

Excellent Communication skills

Strong digital design knowledge.

Exposure to UPF based low power RTL verification.

Prior experience in leading a team is desirable.

Prior experience in PLL verification and Mixed signal verification methodology is highly desirable.

Exposure to digital-analog co-simulations (cosims) is desirable.

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Benefits offered are described: AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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This posting is for an existing vacancy.