Static Timing Analysis (STA) Engineer

Job Description:

Key Responsibilities

• Timing Analysis: Perform static timing analysis for FPGA designs, including setup/hold checks, constraint validation, and timing signoff support.
• Timing Closure Support: Identify, debug, and resolve timing violations in collaboration with RTL, synthesis, and physical design teams.
• Constraint Development: Assist in developing and validating timing constraints to ensure accurate modeling of design intent.
• Cross-Functional Collaboration: Work closely with design, architecture, and implementation teams to improve timing convergence.
• Methodology & Flow Execution: Apply established STA methodologies and contribute to flow improvements and automation where applicable.
• Performance Optimization: Support optimization efforts for performance, power, and area (PPA) through timing-driven analysis.
• Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success. ​