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As a Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology.
Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification.
Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan.
Using system full application to verify performance and identify short falls.
As a Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.
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Independent designer and manufacturer of programmable logic devices.
Visit company websiteJobs and hiring trendsFull-time
Senior · 5+ years experience
Onsite
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