Staff Memory Systems Design Engineer

Detailed Responsibilities (End‑to‑End PCIe for NVMe SSD)

• PHY/MAC IP Review (System Design Perspective)
• Understand criteria for PHY/MAC/controller IP: Gen5/Gen6 readiness, equalization capability, margining hooks, lane mapping flexibility SRNS/SRIS tolerance, clocking modes, power management support Observability: LTSSM state visibility, error counters, replay/NAK stats, equalization telemetry
• Gen5/Gen6 readiness, equalization capability, margining hooks, lane mapping flexibility
• SRNS/SRIS tolerance, clocking modes, power management support
• Observability: LTSSM state visibility, error counters, replay/NAK stats, equalization telemetry
• Review IP documents: Reset sequences, compliance features, link speed change support L1SS behavior, CLKREQ#/REFCLK control expectations AER robustness, surprise down handling, hot/warm reset behavior
• Reset sequences, compliance features, link speed change support
• L1SS behavior, CLKREQ#/REFCLK control expectations
• AER robustness, surprise down handling, hot/warm reset behavior
• Specify platform-facing requirements: Retimer/redriver compatibility assumptions (backplane/adaptor/cables)
• Retimer/redriver compatibility assumptions (backplane/adaptor/cables)
• ASIC/SoC Integration Ownership
• Integrate PCIe subsystem with: Clocking: REFCLK handling, clock request gating, clock-down sequences Resets: PERST# behavior, internal resets, warm/hot resets, FLR support as applicable Power domains: retention strategies, wake sources, D-state coordination Sidebands: WAKE#, CLKREQ#, presence detect patterns (platform dependent)
• Clocking: REFCLK handling, clock request gating, clock-down sequences
• Resets: PERST# behavior, internal resets, warm/hot resets, FLR support as applicable
• Power domains: retention strategies, wake sources, D-state coordination
• Sidebands: WAKE#, CLKREQ#, presence detect patterns (platform dependent)
• Define lane policy: x4 typical NVMe, lane reversal/polarity, width detection & recovery from degraded width
• x4 typical NVMe, lane reversal/polarity, width detection & recovery from degraded width
• PCIe SFR / Register + FW Design Guidelines
• Define a clean SFR map that FW uses for: LTSSM control/observability (state, substate, timers, retries) Link speed/width control and status (negotiated vs target) Low-power triggers: ASPM enable/disable, L1SS policy, L0p policy (if implemented) Clock request & clock gating behavior (safe entry/exit rules) Error logging counters (replay, NAK, ECRC, timeout, malformed TLPs) Recovery controls: link disable/enable, retrain, directed speed change, error clear policy
• LTSSM control/observability (state, substate, timers, retries)
• Link speed/width control and status (negotiated vs target)
• Low-power triggers: ASPM enable/disable, L1SS policy, L0p policy (if implemented)
• Clock request & clock gating behavior (safe entry/exit rules)
• Error logging counters (replay, NAK, ECRC, timeout, malformed TLPs)
• Recovery controls: link disable/enable, retrain, directed speed change, error clear policy
• Provide FW runbooks: “What to do when”: training fails, width reduces, speed fallback, AER floods Safe sequencing across power modes and APST transitions
• “What to do when”: training fails, width reduces, speed fallback, AER floods
• Safe sequencing across power modes and APST transitions
• Link Bring‑Up & Transitions (Sequence Ownership)
• You’ll own/define the exact sequencing rules for:
• Enumeration readiness Ensure config space stability, BAR mapping correctness, MSI/MSI-X readiness timing
• Ensure config space stability, BAR mapping correctness, MSI/MSI-X readiness timing
• Speed negotiation / Directed Speed Change When to allow Gen5/Gen4 fallback; policy for stability vs performance
• When to allow Gen5/Gen4 fallback; policy for stability vs performance
• Width detection & recovery Handling degraded width events (x4 → x2) and reporting/telemetry
• Handling degraded width events (x4 → x2) and reporting/telemetry
• Link power management ASPM policy and its constraints with NVMe latency targets L1 entry/exit triggers and guard timers L1 Substates (L1.1/L1.2) enablement conditions, wake sources, and clock requirements DLRM handling (as applicable to platform/system) with safe NVMe readiness on resume L0p (if supported) and interaction with performance bursts
• ASPM policy and its constraints with NVMe latency targets
• L1 entry/exit triggers and guard timers
• L1 Substates (L1.1/L1.2) enablement conditions, wake sources, and clock requirements
• DLRM handling (as applicable to platform/system) with safe NVMe readiness on resume
• L0p (if supported) and interaction with performance bursts
• Clock down / clock request Define clock request gating conditions, and safe “no transactions in flight” criteria
• Define clock request gating conditions, and safe “no transactions in flight” criteria
• NVMe APST alignment Coordinate NVMe power states (APST) with PCIe L-states so you don’t create: long resume latencies (client) link instability under load (enterprise)
• Coordinate NVMe power states (APST) with PCIe L-states so you don’t create: long resume latencies (client) link instability under load (enterprise)
• long resume latencies (client)
• link instability under load (enterprise)
• Platform Interoperability
• Own differences across laptop and server: Client: aggressive power policies, fast resume, frequent idle entry/exit, D3hot/cold patterns Enterprise: stable performance, high queue depth, error containment, hot-plug-ish behaviors on some platforms
• Client: aggressive power policies, fast resume, frequent idle entry/exit, D3hot/cold patterns
• Enterprise: stable performance, high queue depth, error containment, hot-plug-ish behaviors on some platforms
• Validate across: Multiple root complexes, BIOS implementations, OS stacks
• Multiple root complexes, BIOS implementations, OS stacks
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