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Staff Engineer, VLSI Design Engineering
SanDisk
Karnataka, IND
Full-time
Onsite
Discovered 1 weeks ago
CVerilogSystemVerilogUVMFunctional coverageSystemVerilog Assertions
Free
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Role Overview
The Staff Engineer will lead verification strategy and execution for complex IP blocks, subsystems, and SoC designs.
The role requires 8–11 years of relevant experience and focuses on comprehensive design verification and verification infrastructure.
Key Skills for This Role
CVerilogSystemVerilogUVMFunctional coverageSystemVerilog Assertions
Full Job Posting
About SanDisk
SanDisk develops flash memory and advanced memory technology solutions for consumers and businesses.
The company operates global manufacturing and supply-chain capabilities and focuses on innovation, performance, quality, and sustainability.
Job Overview
The Staff Engineer will lead verification strategy and execution for complex IP blocks, subsystems, and SoC designs.
The role requires 8–11 years of relevant experience and focuses on comprehensive design verification and verification infrastructure.
Job Responsibilities
- Lead development and execution of test plans, verification strategies, and verification infrastructure for complex IP, subsystem, and SoC designs.
- Design UVM verification environments and develop reusable components such as bus functional models, monitors, checkers, and scoreboards.
- Drive functional coverage planning, development, debugging, and closure.
- Develop and maintain SystemVerilog Assertions for design verification.
- Collaborate with architects, RTL designers, and post-silicon validation teams.
- Create verification automation tools and scripts and investigate design failures through root-cause analysis.
- Mentor junior engineers and contribute to improved verification methodologies and best practices.
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