Staff Engineer, Physical Design - Cores

Responsibilities - What you’ll do

• Own Core Implementation: Drive the physical design implementation for high-frequency CPU core blocks and execution pipelines, managing synthesis, place & route, and signoff.
• Engage in Cross-Abstraction-Layer Co-Design: Go beyond standard implementation by actively collaborating with Architecture/RTL/Power for PPA co-optimisation. Understand the CPU microarchitecture to identify logic-depth bottlenecks early and suggest RTL pipelining strategies or structural changes.
• Solve Core-Specific Challenges: Tackle physical bottlenecks unique to CPU cores, including timing closure, datapath placement, routing congestion, complex clock tree synthesis (CTS) for high-speed pipelines, and rigorous dynamic power optimization.
• Aggressive PPA Optimization: Optimize block-level implementation for aggressive Power, Performance, and Area (PPA) goals, managing complex PPA trade-offs to meet target frequencies across various product lines.
• Collaborate Cross-Functionally: Work closely with CPU architecture, RTL design, and Power teams to close design requirements and ensure efficient physical realization of the instruction set architecture.
• Enhance Methodology: Support and improve physical design flows, automation scripts, and methodologies tailored specifically for high-frequency, complex core implementation.

Requirements - What you’ll bring

• 7+ years of hands-on experience in physical design implementation with a proven track record of block-level tape-outs involving high-speed digital logic like CPUs.
• CPU/Datapath Expertise: Specific experience implementing complex control logic, execution units (ALUs, FPUs), or custom data-paths. Familiarity with the physical challenges of pushing high-frequency design limits.
• Cross-Abstraction Awareness: A solid understanding of processor microarchitecture (e.g., instruction pre-fetch, execution units, data forwarding paths). You should be comfortable reading RTL to understand the design intent and collaborate effectively with front-end teams.
• Strong Problem Solving: Proven ability to optimize for aggressive PPA targets using industry-standard physical design techniques, accompanied by a detail-oriented mindset and clear communication of results.
• Tool Proficiency: Hands-on knowledge of RTL to GDS implementation with Synopsys and/or Cadence implementation and sign-off tools.
• Education: Bachelor’s or Master’s in Electrical or Computer Engineering.

Why join us?