Base Career helps you apply smarter for this job.
Key skills for this role
SiFive is looking for a staff level hardware engineer who is passionate about designing industry-leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications.
We’re creating massively customizable IP and improving time-to-market by designing hardware as highly-configurable generators.
We leverage technology and ideas from the software industry to execute hardware design with the agility of software development.
We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP using the Chisel hardware construction library embedded in the Scala language, and are seeking motivated individuals to enhance/evolve our existing IP as well as develop new IP.
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Skip the repetitive application forms
Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.
Trusted by over 500,000 job seekers on Base Career
More from this employer
Santa Clara, USA
Cambridge, GBR
Santa Clara, USA
Cambridge, GBR
Santa Clara, USA
Cambridge, GBR
Santa Clara, USA
Bengaluru, IND
Job Description:
SiFive is looking for a staff level hardware engineer who is passionate about designing industry-leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating massively customizable IP and improving time-to-market by designing hardware as highly-configurable generators. We leverage technology and ideas from the software industry to execute hardware design with the agility of software development.
We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP using the Chisel hardware construction library embedded in the Scala language, and are seeking motivated individuals to enhance/evolve our existing IP as well as develop new IP.
Designing the best interconnect IP in the world, based on the revolutionary open RISC-V and TileLink architectures
Mastering the art of designing hardware as configurable generators in a domain-specific software language for elaborating circuits
Working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance
Knowledge of cache and cache coherency architectures and concepts
Experience with NoC or other interconnect fabrics
Familiarity with industry-standard bus protocols (AXI, AHB, APB, CHI)
Ability to architect solutions to connect bus fabrics of disparate protocols
Strong software engineering skills/background, including: Object-oriented, aspect-oriented, and particularly functional programming Templated metaprogramming, in any language Compiler infrastructures, particularly for domain-specific languages Data modeling, particularly intermediate representations for optimizing or transforming compiler passes Test-driven development, particularly ability to write adaptive unit tests
Object-oriented, aspect-oriented, and particularly functional programming
Templated metaprogramming, in any language
Compiler infrastructures, particularly for domain-specific languages
Data modeling, particularly intermediate representations for optimizing or transforming compiler passes
Test-driven development, particularly ability to write adaptive unit tests
Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL
Attention to detail and a focus on high-quality design
Ability to work well with others and a belief that engineering is a team sport
BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience
Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software
Knowledge of RISC-V architecture
Experience with Git/Github, Jira, Confluence
SiFive is a private RISC-V processor-IP company licensing proprietary cores and technology to chip and system developers.
Visit company websiteJobs and hiring trendsFull-time
Senior
Onsite
Apply faster on company sites with our extension.