Staff Engineer, Physical Design

About the Role

Key Responsibilities- What you’ll do

• Advanced Clock Distribution & Circuit Design: Architect and implement high-speed, low-skew clock distribution networks (e.g., mesh, H-tree, hybrid topologies). Apply circuit-level understanding to optimize clock buffers, clock gaters, latches, and multi-source CTS.
• Interconnect Physical Design: Manage the physical implementation of global signal planning, including high-speed bus routing, long-wire interconnect span limits, and repeater insertion strategies. Optimize long interconnect paths to mitigate RC delay, wire resistance variations, and routing congestion.
• Circuit-Level Timing & Noise Integrity: Leverage a strong fundamental grasp of RC interconnect modeling and transistor-level behavior to resolve deep-submicron physical effects—such as crosstalk delay, Electromigration (EM), and dynamic IR-drop on clock and global signal lines.
• Architectural & Circuit Co-Optimization: Partner with RTL and Architecture teams to influence design decisions. Bridge the gap between logic design and circuit reality, identifying bottlenecks early (such as asynchronous clock domain crossings and interconnect span limits) and suggesting structural or microarchitectural optimizations.
• Technical Leadership & Signoff: Act as the subject matter expert for interconnect structures, clock planning, and circuit techniques during implementation. Mentor junior engineers and contribute to the evolution of advanced design methodologies and flows.

Requirements - What you’ll bring

• Experience: 8+ years of hands-on physical design experience with a proven track record of successful tape-outs on advanced process nodes (7nm and below preferred).
• Clocking & Interconnect Expertise: Deep familiarity with the physical implementation of advanced clocking structures, global interconnect routing, multi-corner multi-mode (MCMM) timing closure, and jitter analysis.
• Circuit-Level Understanding: Strong fundamentals in VLSI design, including CMOS circuit behavior, RC delay networks and transistor-level timing/noise concepts.
• Tool Mastery: Expert-level proficiency with industry-standard EDA tools—specifically Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) implementation and sign-off tools, with heavy emphasis on CTS, parasitic extraction (RC), and Static Timing Analysis (STA) engines.
• Problem Solving: Ability to debug complex timing violations, cross-talk delay, global interconnect routing congestion, and transient IR drop issues with minimal supervision.
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Why join us?